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this document provides detailed information on power considerations, dc/ac electrical characteristics, and ac timing speci?cations for the mpc857t (refer to table 1). the mpc857t contains a powerpc? processor core. this document contains the following topics: topic page part i, overview 1 part ii, features 2 part iii, maximum tolerated ratings 6 part iv, thermal characteristics 7 part v, power dissipation 8 part vi, dc characteristics 9 part vii, thermal calculation and measurement 10 part viii, layout practices 12 part ix, bus signal timing 13 part x, ieee 1149.1 electrical speci?cations 40 part xi, cpm electrical characteristics 41 part xii, utopia ac electrical speci?cations 64 part xiii, fec electrical characteristics 65 part xiv, mechanical data and ordering information 68 part xv, document revision history 81 part i overview the mpc857t is a derivative of motorolas mc68360 quad integrated communications controller (quicc?) and part of the powerquicc? family of devices. it is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. the mpc8577t provides enhanced atm functionality over that of other atm-enabled members of the mpc860 family. the cpu on the mpc857t is a 32-bit mpc8xx core that incorporates memory management units (mmus) and instruction and data caches. the communications processor module (cpm) from the mc68360 quicc has been enhanced by the addition of the inter-integrated controller (i 2 c) channel. the memory controller has been enhanced, enabling the mpc857t advance information mpc857tec/d rev. 0.4, 5/2003 mpc857t hardware speci?ations
2 mpc857t hardware speci?cations motorola features features to support any type of memory, including high-performance memories and new types of drams. a pcmcia socket controller supports up to two sockets. a real-time clock has also been integrated. table 1 shows the functionality supported by the mpc857t and mpc857dsl. unless otherwise speci?ed, the powerquicc unit is referred to as the mpc857t in this document. part ii features the following list summarizes the key mpc857t features: ? embedded single-issue, 32-bit mpc8xx core (implementing the powerpc architecture) with thirty-two 32-bit general-purpose registers (gprs) the core performs branch prediction with conditional prefetch, without conditional execution 4-kbyte data cache and 4- kbyte instruction cache (see table 1). C 4-kbyte instruction cache is two-way, set-associative with 128 sets. C 4-kbyte data cache is two-way, set-associative with 128 sets. C cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. C caches are physically addressed, implement a least recently used (lru) replacement algorithm, and are lockable on a cache block basis. mmu with 32-entry tlb, fully associative instruction and data tlbs mmu supports multiple page sizes of 4, 16, and 512 kbytes, and 8 mbytes; 16 virtual address spaces and 16 protection groups advanced on-chip-emulation debug mode ? the mpc857t provides enhanced atm functionality over that of the mpc860sar. the mpc857t adds major new features available in enhanced sar (esar) mode, including the following: multiple apc priority levels available to support a range of traf?c pace requirements port-to-port switching capability without the need for ram-based microcode simultaneous mii (100base-t) and utopia (half-duplex) capability optional statistical cell counters per phy parameter ram for both spi and i 2 c can be relocated without ram-based microcode. supports full-duplex utopia master (atm side) operation using a split bus ? up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) ? 32 address lines ? operates at up to 80 mhz ? memory controller (eight banks) table 1. mpc857t functionality part cache ethernet scc instruction cache data cache 10t 10/100 mpc857t 4 kbyte 4 kbyte up to 4 1 1 mpc857dsl 4 kbyte 4 kbyte up to 4 1 1
motorola mpc857t hardware speci?cations 3 features contains complete dynamic ram (dram) controller each bank can be a chip select or ras to support a dram bank up to 30 wait states programmable per memory bank glueless interface to dram, simms, sram, eproms, ?ash eproms, and other memory devices. dram controller programmable to support most size and speed memory interfaces four cas lines, four we lines, one oe line boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) variable block sizes (32 kbyteC256 mbyte) selectable write protection on-chip bus arbitration logic ? general-purpose timers four 16-bit timers or two 32-bit timers gate mode can enable/disable counting interrupt can be masked on reference match and event capture ? fast ethernet controller (fec) simultaneous mii (100base-t) and utopia operation when using the utopia multiplexed bus. ? system integration unit (siu) bus monitor software watchdog periodic interrupt timer (pit) low-power stop mode clock synthesizer decrementer, time base, and real-time clock (rtc) from the powerpc architecture reset controller ieee 1149.1 test access port (jtag) ? interrupts seven external interrupt request (irq) lines 12 port pins with interrupt capability 20 internal interrupt sources programmable highest priority request ? communications processor module (cpm) risc controller communication-speci?c commands (for example, graceful stop transmit , enter hunt mode , and restart transmit ) supports continuous mode transmission and reception on all serial channels up to 8-kbytes of dual-port ram 10 serial dma (sdma) channels three parallel i/o registers with open-drain capability ? four baud rate generators
4 mpc857t hardware speci?cations motorola features features independent (can be connected to any scc or smc) allow changes during operation autobaud support option ? one scc (serial communication controller) (the mpc857dsl supports ethernet only) serial atm capability ethernet/ieee 802.3 supporting full 10-mbps operation hdlc/sdlc hdlc bus (implements an hdlc-based local area network (lan)) asynchronous hdlc to support ppp (point-to-point protocol) appletalk universal asynchronous receiver transmitter (uart) synchronous uart serial infrared (irda) binary synchronous communication (bisync) totally transparent (bit streams) totally transparent (frame based with optional cyclic redundancy check (crc)) ? two smcs (serial management channels) (the mpc857dsl has one smc, for uart) uart transparent general circuit interface (gci) controller can be connected to the time-division multiplexed (tdm) channel ? one serial peripheral interface (spi) supports master and slave modes supports multiple-master operation on the same bus ? one inter-integrated circuit (i 2 c) port supports master and slave modes multiple-master environment support ? time-slot assigner (tsa) (the mpc857dsl does not have the tsa) allows scc and smcs to run in multiplexed and/or non-multiplexed operation supports t1, cept, pcm highway, user de?ned 1- or 8-bit resolution allows independent transmit and receive routing, frame synchronization, clocking allows dynamic changes can be internally connected to three serial channels (one scc and two smcs) ? parallel interface port (pip) centronics interface support supports fast connection between compatible ports on mpc857t or mc68360 ? pcmcia interface master (socket) interface, release 2.1 compliant supports two independent pcmcia sockets
motorola mpc857t hardware speci?cations 5 features 8 memory or i/o windows supported ? low power support full onall units fully powered dozecore functional units disabled except time base decrementer, pll, memory controller, rtc, and cpm in low-power standby sleepall units disabled except rtc, pit, time base, and decrementer with pll active for fast wake up deep sleepall units disabled including pll except rtc, pit, time base, and decrementer. power down mode all units powered down except pll, rtc, pit, time base and decrementer ? debug interface eight comparators: four operate on instruction address, two operate on data address, and two operate on data supports conditions: = < > each watchpoint can generate a break point internally ? 3.3 v operation with 5-v ttl compatibility except extal and extclk ? 357-pin ball grid array (bga) package the mpc857t is comprised of three modules that each use the 32-bit internal busthe mpc8xx core, the system integration unit (siu), and the communication processor module (cpm). the mpc857t block diagram is shown in figure 1.
6 mpc857t hardware speci?cations motorola maximum tolerated ratings maximum tolerated ratings figure 1. mpc857t block diagram note the mpc857dsl does not contain smc2 nor the time slot assigner, and provides eight sdma channels. part iii maximum tolerated ratings this section provides the maximum tolerated voltage and temperature ranges for the mpc857t. table 2 provides the maximum ratings. bus system interface unit (siu) embedded parallel i/o memory controller 4 timers interrupt controllers 8-kbyte dual-port ram 10 virtual serial and 2 independent dma channels system functions real-time clock pcmcia/ata interface 4-kbyte instruction cache 32-entry itlb instruction mmu 4-kbyte data cache 32-entry dtlb data mmu instruction bus load/store bus unified 4 baud rate generators parallel interface port and utopia internal bus interface unit external bus interface unit timers 32-bit risc controller and program rom scc1 serial interface i2c spi smc2* smc1 time slot assigner mpc8xx processor core dmas fifos 10/100 mii base-t media scc1 serial interface i2c spi smc1 time slot assigner fast ethernet controller control access
motorola mpc857t hardware speci?cations 7 thermal characteristics this device contains circuitry protecting against damage due to high-static voltage or electrical ?elds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either gnd or v cc ). part iv thermal characteristics table 3 shows the thermal characteristics for the mpc857t. table 2. maximum tolerated ratings (gnd = 0v) rating symbol value unit supply voltage 1 1 the power supply of the device must start its ramp from 0.0 v. vddh -0.3 to 4.0 v vddl -0.3 to 4.0 v kapwr -0.3 to 4.0 v vddsyn -0.3 to 4.0 v input voltage 2 2 functional operating conditions are provided with the dc electrical speci?cations in table 5. absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. caution : all inputs cannot be more than 2.5 v greater than the supply voltage. this restriction applies to power-up and normal operation (that is, if the mpc857t is unpowered, voltage greater than 2.5 v must not be applied to its inputs). v in gnd-0.3 to vddh v temperature 3 (standard) 3 minimum temperatures are guaranteed as ambient temperature, t a . maximum temperatures are guaranteed as junction temperature, t j . t a(min) 0?c t j(max) 95 ?c temperature 3 (extended) t a(min) -40 ?c t j(max) 105 ?c storage temperature range t stg -55 to +150 ?c
8 mpc857t hardware speci?cations motorola power dissipation power dissipation part v power dissipation table 4 provides power dissipation information. the modes are 1:1, where cpu and bus speeds are equal, and 2:1 mode, where cpu frequency is twice bus speed. table 3. mpc857t thermal resistance data rating environment symbol value unit junction to ambient 1 1 junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air ?ow, power dissipation of other components on the board, and board thermal resistance. natural convection single layer board (1s) r ja 2 2 per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. 40 c/w four layer board (2s2p) r jma 3 3 per jedec jesd51-6 with the board horizontal. 25 air ?ow (200 ft/min) single layer board (1s) r jma 3 32 four layer board (2s2p) r jma 3 21 junction to board 4 4 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. r jb 15 junction to case 5 5 indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. for exposed pad packages where the pad would be expected to be soldered, junction to case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance. r jc 7 junction to package top 6 6 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. natural convection jt 2 air ?ow (200 ft/min) jt 3 table 4. power dissipation (p d ) die revision frequency typical 1 1 typical power dissipation is measured at 3.3v. maximum 2 2 maximum power dissipation is measured at 3.5v. note values in table 4 represent vddl based power dissipation and do not include i/o power dissipation over vddh. i/o power dissipation varies widely by application due to buffer current, depending on external circuitry. unit 0 (1:1 mode) 50 mhz 656 735 mw 66 mhz tbd tbd mw 0 (2:1 mode) 66 mhz 722 762 mw 80 mhz 851 909 mw
motorola mpc857t hardware speci?cations 9 dc characteristics part vi dc characteristics table 5 provides the dc electrical characteristics for the mpc857t. table 5. dc electrical speci?cations characteristic symbol min max uni t operating voltage at 40 mhz or less vddh, vddl, vddsyn 3.0 3.6 v kapwr (power-down mode) 2.0 3.6 v kapwr (all other operating modes) vddh - 0.4 vddh v operating voltage greater than 40 mhz vddh, vddl, kapwr, vddsyn 3.135 3.465 v kapwr (power-down mode) 2.0 3.6 v kapwr (all other operating modes) vddh - 0.4 vddh v input high voltage (all inputs except extal and extclk) vih 2.0 5.5 v input low voltage vil gnd 0.8 v extal, extclk input high voltage vihc 0.7*(vcc) vcc+0.3 v input leakage current, vin = 5.5v (except tms, trst , dsck and dsdi pins) i in 100 a input leakage current, vin = 3.6v (except tms, trst , dsck, and dsdi) i in 10a input leakage current, vin = 0v (except tms, trst , dsck and dsdi pins) i in 10a input capacitance 1 1 input capacitance is periodically sampled. c in 20pf output high voltage, ioh = -2.0 ma, vddh = 3.0v except xtal, xfc, and open drain pins voh 2.4 v output low voltage iol = 2.0 ma (clkout) iol = 3.2 ma 2 iol = 5.3 ma 3 iol = 7.0 ma (txd1/pa14, pa12) iol = 8.9 ma (ts , t a , tea , bi , bb , hreset , sreset ) 2 a(0:31), tsiz0/reg , tsiz1, d(0:31), dp(0:3)/irq (3:6), rd/wr , b urst , rsv /irq2 , ip_b(0:1)/iwp(0:1)/vfls(0:1), ip_b2/iois16_b/at2, ip_b3/iwp2/vf2, ip_b4/lwp0/vf0, ip_b5/lwp1/vf1, ip_b6/dsdi/at0, ip_b7/ptr/at3, rxd1 /pa15, pa13, pa11, pa10, l1txda/pa9, l1rxda/pa8, tin1/l1rclka/brgo1/clk1/pa7, brgclk1/t out1 /clk2/pa6, tin2/l1tclka/brgo2/clk3/pa5, t out2 /clk4/pa4, tin3/brgo3/clk5/pa3, brgclk2/t out3 /clk6/pa2, tin4/brgo4/clk7/pa1, t out4 /clk8/pa0, rejct1 /spisel /pb31, spiclk/pb30, spimosi/pb29, brgo4/spimiso/pb28, brgo1/i2csda/pb27, brgo2/i2cscl/pb26, smtxd1/pb25, smrxd1/pb24, smsyn1 /sd a ck1 /pb23, smsyn2 /sd a ck2 /pb22, smtxd2/pb21, smrxd2/l1clkoa/pb20, l1st1/r ts1 /pb19, l1st2/pb18, l1st3/pb17, l1st4/l1rqa /pb16, brgo3/pb15, rstr t1 /pb14, l1st1/r ts1 /dreq0 /pc15, l1st2/dreq1 /pc14, l1st3/pc13, l1st4/l1rqa /pc12, cts1 /pc11, tga te1 /cd1 /pc10, pc9, tga te2 /pc8, sd a ck2 /pc7, pc6, sd a ck1 /l1tsynca/pc5, l1rsynca/pc4, pd15, pd14, pd13, pd12, pd11, pd10, pd9, pd8, pd5, pd6, pd7, pd4, pd3, mii_mdc, mii_tx_er, mii_en, mii_mdio, mii_txd[0:3] vol 0.5 v
10 mpc857t hardware speci?cations motorola thermal calculation and measurementestimation with junction-to-ambient thermal resistance thermal calculation and measurementestimation with junction-to-ambient thermal resistance part vii thermal calculation and measurement for the following discussions, p d = (vdd x idd) + pi/o, where pi/o is the power dissipation of the i/o drivers. 7.1estimation with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , in c can be obtained from the equation: t j = t a +( r ja x p d ) where: t a = ambient temperature oc r ja = package junction-to-ambient thermal resistance (oc/w) p d = power dissipation in package the junction-to-ambient thermal resistance is an industry standard value which provides a quick and easy estimation of thermal performance. however, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity t j -t a ) are possible. 7.2 estimation with junction-to-case thermal resistance historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r ja = r jc + r ca where: r ja = junction-to-ambient thermal resistance (oc/w) r jc = junction-to-case thermal resistance (oc/w) r ca = case-to-ambient thermal resistance (oc/w) r jc is device related and cannot be in?uenced by the user. the user adjusts the thermal environment to affect the case-to-ambient thermal resistance, r ca . for instance, the user can change the air ?ow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat ?ows through the case and the heat sink to the ambient environment. for most packages, a better model is required. 3 bdip /gpl_b (5), br , bg , frz/irq6 , cs (0:5), cs (6)/ce (1)_b, cs (7)/ce (2)_b, we0 /bs _b0/iord , we1 /bs _b1/io wr , we2 /bs _b2/pcoe , we3 /bs _b3/pcwe , bs _a(0:3), gpl_a0 /gpl_b0 , oe /gpl_a1 /gpl_b1 , gpl_a (2:3)/gpl_b (2:3)/cs (2:3), upwaita/gpl_a4 , upwaitb/gpl_b4 , gpl_a5 , ale_a, ce 1_a, ce 2_a, ale_b/dsck/at1, op(0:1), op2/modck1/sts , op3/modck2/dsdo, baddr(28:30)
motorola mpc857t hardware speci?cations 1 1 thermal calculation and measurementestimation with junction-to-board thermal resistance 7.3 estimation with junction-to-board thermal resistance a simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a two resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. the junction-to-case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. it has been observed that the thermal performance of most plastic packages and especially pbga packages is strongly dependent on the board temperature; see figure 2. figure 2. effect of board temperature rise on thermal behavior if the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: t j = t b +( r jb x p d ) where: r jb = junction-to-board thermal resistance (oc/w) t b = board temperature oc p d = power dissipation in package if the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. for this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane. 0 10 20 30 40 50 60 70 80 90 100 0 2040 6080 board temperture rise above ambient divided by package power junction temperature rise above ambient divided by package power
12 mpc857t hardware speci?cations motorola layout practicesestimation using simulation layout practicesestimation using simulation 7.4 estimation using simulation when the board temperature is not known, a thermal simulation of the application is needed. the simple two resistor model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the package can be used in the thermal simulation. 7.5 experimental determination to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t +( jt x p d ) where: jt = thermal characterization parameter t t = thermocouple temperature on top of package p d = power dissipation in package the thermal characterization parameter is measured per jesd51-2 speci?cation published by jedec using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed ?at against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 7.6 references semiconductor equipment and materials international (415) 964-5111 805 east middle?eld rd mountain view, ca 94043 mil-spec and eia/jesd (jedec) speci?cations 800-854-7179 or (available from global engineering documents) 303-397-7956 jedec speci?cations http://www.jedec.org 1. c.e. triplett and b. joiner, an experimental characterization of a 272 pbga within an automotive engine controller module, proceedings of semitherm, san diego, 1998, pp. 47-54. 2. b. joiner and v. adams, measurement and simulation of junction to board thermal resistance and its application in thermal modeling, proceedings of semitherm, san diego, 1999, pp. 212-220. part viii layout practices each v cc pin on the mpc857t should be provided with a low-impedance path to the boards supply. each gnd pin should likewise be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the v cc power supply should be bypassed to ground using at least four 0.1 f by-pass capacitors located as close as possible to the four sides of the package. the capacitor leads and associated printed circuit traces connecting to chip v cc and gnd should be kept to less than half an inch per capacitor lead. a four-layer board is recommended, employing two inner layers as v cc and gnd planes.
motorola mpc857t hardware speci?cations 1 3 bus signal timingreferences all output pins on the mpc857t have fast rise and fall times. printed circuit (pc) trace interconnection length should be minimized in order to minimize undershoot and re?ections caused by these fast output switching times. this recommendation particularly applies to the address and data busses. maximum pc trace lengths of six inches are recommended. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the v cc and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins. part ix bus signal timing table 6 provides the bus operation timing for the mpc857t at 33 mhz, 40 mhz, 50 mhz and 66 mhz. the maximum bus speed supported by the mpc857t is 66 mhz. higher-speed parts must be operated in half-speed bus mode (for example, an mpc857t used at 80mhz must be con?gured for a 40 mhz bus). the timing for the mpc857t bus shown assumes a 50-pf load for maximum delays and a 0-pf load for minimum delays. table 6. bus operation timings num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max b1 clkout period 30.30 30.30 25.00 30.30 20.00 30.30 15.15 30.30 ns b1a extclk to clkout phase skew (extclk > 15 mhz and mf <= 2) -0.90 0.90 -0.90 0.90 -0.90 0.90 -0.90 0.90 ns b1b extclk to clkout phase skew (extclk > 10 mhz and mf < 10) -2.30 2.30 -2.30 2.30 -2.30 2.30 -2.30 2.30 ns b1c clkout phase jitter (extclk > 15 mhz and mf <= 2) 1 -0.60 0.60 -0.60 0.60 -0.60 0.60 -0.60 0.60 ns b1d clkout phase jitter 1 -2.00 2.00 -2.00 2.00 -2.00 2.00 -2.00 2.00 ns b1e clkout frequency jitter (mf < 10) 1 0.50 0.50 0.50 0.50 % b1f clkout frequency jitter (10 < mf < 500) 1 2.00 2.00 2.00 2.00 % b1g clkout frequency jitter (mf > 500) 1 3.00 3.00 3.00 3.00 % b1h frequency jitter on extclk 2 0.50 0.50 0.50 0.50 % b2 clkout pulse width low 12.12 10.00 8.00 6.06 ns b3 clkout width high 12.12 10.00 8.00 6.06 ns b4 clkout rise time 3 4.00 4.00 4.00 4.00 ns b5 33 clkout fall time 3 4.00 4.00 4.00 4.00 ns b7 clkout to a(0:31), baddr(28:30), rd/wr , b urst , d(0:31), dp(0:3) invalid 7.58 6.25 5.00 3.80 ns b7a clkout to tsiz(0:1), reg , rsv , at(0:3), bdip , ptr invalid 7.58 6.25 5.00 3.80 ns
14 mpc857t hardware speci?cations motorola bus signal timingreferences bus signal timingreferences b7b clkout to br , bg , frz, vfls(0:1), vf(0:2) iwp(0:2), lwp(0:1), sts invalid 4 7.58 6.25 5.00 3.80 ns b8 clkout to a(0:31), baddr(28:30) rd/wr , b urst , d(0:31), dp(0:3) valid 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns b8a clkout to tsiz(0:1), reg , rsv , at(0:3) bdip , ptr valid 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns b8b clkout to br , bg , vfls(0:1), vf(0:2), iwp(0:2), frz, lwp(0:1), sts valid 4 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns b9 clkout to a(0:31), baddr(28:30), rd/wr , b urst , d(0:31), dp(0:3), tsiz(0:1), reg , rsv , at(0:3), ptr high-z 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns b11 clkout to ts , bb assertion 7.58 13.58 6.25 12.25 5.00 11.00 3.80 11.29 ns b11 a clkout to t a , bi assertion (when driven by the memory controller or pcmcia interface) 2.50 9.25 2.50 9.25 2.50 9.25 2.50 9.75 ns b12 clkout to ts , bb negation 7.58 14.33 6.25 13.00 5.00 11.75 3.80 8.54 ns b12 a clkout to t a , bi negation (when driven by the memory controller or pcmcia interface) 2.50 11.00 2.50 11.00 2.50 11.00 2.50 9.00 ns b13 clkout to ts , bb high-z 7.58 21.58 6.25 20.25 5.00 19.00 3.80 14.04 ns b13 a clkout to t a , bi high-z (when driven by the memory controller or pcmcia interface) 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns b14 clkout to tea assertion 2.50 10.00 2.50 10.00 2.50 10.00 2.50 9.00 ns b15 clkout to tea high-z 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns b16 t a , bi valid to clkout (setup time) 9.75 9.75 9.75 6.00 ns b16 a tea , kr , retr y , cr valid to clkout (setup time) 10.00 10.00 10.00 4.50 ns b16 b bb , bg , br , valid to clkout (setup time) 5 8.50 8.50 8.50 4.00 ns b17 clkout to t a , tea , bi , bb , bg , br valid (hold time). 1.00 1.00 1.00 2.00 ns b17 a clkout to kr , retr y , cr valid (hold time) 2.00 2.00 2.00 2.00 ns b18 d(0:31), dp(0:3) valid to clkout rising edge (setup time) 6 6.00 6.00 6.00 6.00 ns table 6. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
motorola mpc857t hardware speci?cations 1 5 bus signal timingreferences b19 clkout rising edge to d(0:31), dp(0:3) valid (hold time) 6 1.00 1.00 1.00 2.00 ns b20 d(0:31), dp(0:3) valid to clkout falling edge (setup time) 7 4.00 4.00 4.00 4.00 ns b21 clkout falling edge to d(0:31), dp(0:3) valid (hold time) 7 2.00 2.00 2.00 2.00 ns b22 clkout rising edge to cs asserted gpcm acs = 00 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns b22 a clkout falling edge to cs asserted gpcm acs = 10, trlx = 0 8.00 8.00 8.00 8.00 ns b22 b clkout falling edge to cs asserted gpcm acs = 11, trlx = 0, ebdf = 0 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns b22 c clkout falling edge to cs asserted gpcm acs = 11, trlx = 0, ebdf = 1 10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns b23 clkout rising edge to cs negated gpcm read access, gpcm write access acs = 00, trlx = 0 & csnt = 0 2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns b24 a(0:31) and baddr(28:30) to cs asserted gpcm acs = 10, trlx = 0. 5.58 4.25 3.00 1.79 ns b24 a a(0:31) and baddr(28:30) to cs asserted gpcm acs = 11 trlx = 0 13.15 10.50 8.00 5.58 ns b25 clkout rising edge to oe , we (0:3) asserted 9.00 9.00 9.00 9.00 ns b26 clkout rising edge to oe negated 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns b27 a(0:31) and baddr(28:30) to cs asserted gpcm acs = 10, trlx = 1 35.88 29.25 23.00 16.94 ns b27 a a(0:31) and baddr(28:30) to cs asserted gpcm acs = 11, trlx = 1 43.45 35.50 28.00 20.73 ns b28 clkout rising edge to we (0:3) negated gpcm write access csnt = 0 9.00 9.00 9.00 9.00 ns b28 a clkout falling edge to we (0:3) negated gpcm write access trlx = 0, csnt = 1, ebdf = 0 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns b28 b clkout falling edge to cs negated gpcm write access trlx = 0, csnt = 1 acs = 10 or acs = 11, ebdf = 0 14.33 13.00 11.75 10.54 ns b28 c clkout falling edge to we (0:3) negated gpcm write access trlx = 0, csnt = 1 write access trlx = 0, csnt = 1, ebdf = 1 10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns table 6. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
16 mpc857t hardware speci?cations motorola bus signal timingreferences bus signal timingreferences b28 d clkout falling edge to cs negated gpcm write access trlx = 0, csnt = 1, acs = 10, or acs = 11, ebdf = 1 17.99 16.00 14.13 12.31 ns b29 we (0:3) negated to d(0:31), dp(0:3) high-z gpcm write access, csnt = 0, ebdf = 0 5.58 4.25 3.00 1.79 ns b29 a we (0:3) negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 0, csnt = 1, ebdf = 0 13.15 10.5 8.00 5.58 ns b29 b cs negated to d(0:31), dp(0:3), high z gpcm write access, acs = 00, trlx = 0 & csnt = 0 5.58 4.25 3.00 1.79 ns b29 c cs negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 0, csnt = 1, acs = 10, or acs = 11 ebdf = 0 13.15 10.5 8.00 5.58 ns b29 d we (0:3) negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 1, csnt = 1, ebdf = 0 43.45 35.5 28.00 20.73 ns b29 e cs negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 1, csnt = 1, acs = 10, or acs = 11 ebdf = 0 43.45 35.5 28.00 29.73 ns b29f we (0:3) negated to d(0:31), dp(0:3) high z gpcm write access, trlx = 0, csnt = 1, ebdf = 1 8.86 6.88 5.00 3.18 ns b29 g cs negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 0, csnt = 1 acs = 10 or acs = 11, ebdf = 1 8.86 6.88 5.00 3.18 ns b29 h we (0:3) negated to d(0:31), dp(0:3) high z gpcm write access, trlx = 1, csnt = 1, ebdf = 1 38.67 31.38 24.50 17.83 ns b29i cs negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 1, csnt = 1, acs = 10 or acs = 11, ebdf = 1 38.67 31.38 24.50 17.83 ns b30 cs , we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access 8 5.58 4.25 3.00 1.79 ns b30 a we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm, write access, trlx = 0, csnt = 1, cs negated to a(0:31) invalid gpcm write access trlx = 0, csnt =1 acs = 10, or acs == 11, ebdf = 0 13.15 10.50 8.00 5.58 ns table 6. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
motorola mpc857t hardware speci?cations 1 7 bus signal timingreferences b30 b we (0:3) negated to a(0:31) invalid gpcm baddr(28:30) invalid gpcm write access, trlx = 1, csnt = 1. cs negated to a(0:31) invalid gpcm write access trlx = 1, csnt = 1, acs = 10, or acs == 11 ebdf = 0 43.45 35.50 28.00 20.73 ns b30 c we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access, trlx = 0, csnt = 1. cs negated to a(0:31) invalid gpcm write access, trlx = 0, csnt = 1 acs = 10, acs == 11, ebdf = 1 8.36 6.38 4.50 2.68 ns b30 d we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access trlx = 1, csnt =1, cs negated to a(0:31) invalid gpcm write access trlx = 1, csnt = 1, acs = 10 or 11, ebdf = 1 38.67 31.38 24.50 17.83 ns b31 clkout falling edge to cs valid - as requested by control bit cst4 in the corresponding word in the upm 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns b31 a clkout falling edge to cs valid - as requested by control bit cst1 in the corresponding word in the upm 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns b31 b clkout rising edge to cs valid - as requested by control bit cst2 in the corresponding word in the upm 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns b31 c clkout rising edge to cs valid- as requested by control bit cst3 in the corresponding word in the upm 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns b31 d clkout falling edge to cs valid, as requested by control bit cst1 in the corresponding word in the upm ebdf = 1 13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns b32 clkout falling edge to bs valid- as requested by control bit bst4 in the corresponding word in the upm 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns b32 a clkout falling edge to bs valid - as requested by control bit bst1 in the corresponding word in the upm, ebdf = 0 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns b32 b clkout rising edge to bs valid - as requested by control bit bst2 in the corresponding word in the upm 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns table 6. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
18 mpc857t hardware speci?cations motorola bus signal timingreferences bus signal timingreferences b32 c clkout rising edge to bs valid - as requested by control bit bst3 in the corresponding word in the upm 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns b32 d clkout falling edge to bs valid- as requested by control bit bst1 in the corresponding word in the upm, ebdf = 1 13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns b33 clkout falling edge to gpl valid - as requested by control bit gxt4 in the corresponding word in the upm 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns b33 a clkout rising edge to gpl valid - as requested by control bit gxt3 in the corresponding word in the upm 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns b34 a(0:31), baddr(28:30), and d(0:31) to cs valid - as requested by control bit cst4 in the corresponding word in the upm 5.58 4.25 3.00 1.79 ns b34 a a(0:31), baddr(28:30), and d(0:31) to cs valid - as requested by control bit cst1 in the corresponding word in the upm 13.15 10.50 8.00 5.58 ns b34 b a(0:31), baddr(28:30), and d(0:31) to cs valid - as requested by cst2 in the corresponding word in upm 20.73 16.75 13.00 9.36 ns b35 a(0:31), baddr(28:30) to cs valid - as requested by control bit bst4 in the corresponding word in the upm 5.58 4.25 3.00 1.79 ns b35 a a(0:31), baddr(28:30), and d(0:31) to bs valid - as requested by bst1 in the corresponding word in the upm 13.15 10.50 8.00 5.58 ns b35 b a(0:31), baddr(28:30), and d(0:31) to bs valid - as requested by control bit bst2 in the corresponding word in the upm 20.73 16.75 13.00 9.36 ns b36 a(0:31), baddr(28:30), and d(0:31) to gpl valid as requested by control bit gxt4 in the corresponding word in the upm 5.58 4.25 3.00 1.79 ns b37 upwait valid to clkout falling edge 9 6.00 6.00 6.00 6.00 ns b38 clkout falling edge to upwait valid 9 1.00 1.00 1.00 1.00 ns b39 as valid to clkout rising edge 10 7.00 7.00 7.00 7.00 ns table 6. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
motorola mpc857t hardware speci?cations 1 9 bus signal timingreferences figure 3 is the control timing diagram. b40 a(0:31), tsiz(0:1), rd/wr , b urst , valid to clkout rising edge 7.00 7.00 7.00 7.00 ns b41 ts valid to clkout rising edge (setup time) 7.00 7.00 7.00 7.00 ns b42 clkout rising edge to ts valid (hold time) 2.00 2.00 2.00 2.00 ns b43 as negation to memory controller signals negation tbd tbd tbd tbd ns 1 phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value. 2 if the rate of change of the frequency of extal is slow (i.e. it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then the maximum allowed jitter on extal can be up to 2%. 3 the timings speci?ed in b4 and b5 are based on full strength clock. 4 the timing for br output is relevant when the mpc857t is selected to work with external bus arbiter. the timing for bg output is relevant when the mpc857t is selected to work with internal bus arbiter. 5 the timing required for br input is relevant when the mpc857t is selected to work with internal bus arbiter. the timing for bg input is relevant when the mpc857t is selected to work with external bus arbiter. 6 the d(0:31) and dp(0:3) input timings b18 and b19 refer to the rising edge of the clkout in which the t a input signal is asserted. 7 the d(0:31) and dp(0:3) input timings b20 and b21 refer to the falling edge of the clkout. this timing is valid only for read accesses controlled by chip-selects under control of the upm in the memory controller, for data beats where dlt3 = 1 in the upm ram words. (this is only the case where data is latched on the falling edge of clkout.) 8 the timing b30 refers to cs when acs = 00 and to we (0:3) when csnt = 0. 9 the signal upwait is considered asynchronous to the clkout and synchronized internally. the timings speci?ed in b37 and b38 are speci?ed to enable the freeze of the upm output signals as described in figure 18. 10 the as signal is considered asynchronous to the clkout. the timing b39 is speci?ed in order to allow the behavior speci?ed in figure 21. table 6. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
20 mpc857t hardware speci?cations motorola bus signal timingreferences bus signal timingreferences figure 3. control timing figure 4 provides the timing for the external clock. figure 4. external clock timing figure 5 provides the timing for the synchronous output signals.

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